Shift register in this paper possess low efficient SSASPL (Static differential Sense Amp Shared Pulsed Latch). Timing problem between pulsed latches is solved using multiple non-overlap delayed strobe signal. Here latches are grouped into several sub-shift registers. To provide better results, leakage current and leakage power are reduced with MTCMOS (Multi Threshold Complementary Metal Oxide Semiconductor) and power-delay products are further reduced using Mod-GDI(Modified Gate Diffusion Input) technique. A 16-bit shift register in 22nm technology with supply voltage VDD =200mv and consumes 0.147mW. Power consumption in percentage is 43.04% in other words power reduced in comparison to the existing systems is 14.85%. Simulation is done using Tanner EDA TOOL in 22nm technology.