A novel design methodology is to implement a secure DPA resistant crypto secured processor such as advanced encryption standard (AES) and triple data encryption standard (DES), by secure side-channel attacks, such as differential power analysis (DPA). The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. Dynamic logic is obfuscates the output waveforms and the circuit operation, which reducing the effectiveness of the DPA attack for mitigating DPA attacks for applications of secure integrated circuit (IC) design. A Penta MTJ gate that provides self-referencing, simple cascading, less voltage headroom downside in pre charge sense electronic equipment and low space. These types of gate is implemented in (PADDL). Different logic gates and different writing circuitry is required, but the sensing portion is remains same. Therefore, the information is deposited in the pinned layers using series or parallel combinations of transistors as per the logic storing in the Penta MTJ. The logic gate is authenticated by simulation at the 22nm technology node using a tanner tool.

Content addressable memories (CAMs) are type of computer memory that is used in search intensive applications. It involves content based searching. The conventional CAM is designed using MOSFET, due to which the power consumption is very high because of parallel architecture and short channel Effects such as leakage current. However, the current trend is to use a new non planar device architecture, the so called FinFET to overcome the problems of planar MOSFET stated above. Among the alternatives to planar MOSFET, FinFET is proved to be more efficient in terms of power. Although the CAM using FinFET is efficient ,it is volatile. In order to make it non-volatile, a new element called memristor can be used. Also, when the device is idle,the leakage will be high. This can be overcome by the use of MT-CMOS for power gating. This paper proposes a novel design of NOR content addressable memory bit cell using memristor and MT-CMOS in 22-nm FinFET Technology. The design has been simulated in 22nm FinFET technology using Tanner EDA tool.