Volume 30, Issue 3, May 2017, Pages 343–348
V.P. Krishnammal1, S. Anbuselvi2, and K. Janani3
1 ASST PROF/EIE /ACE, India
2 UG STUDENT/ EIE/ACE, India
3 UG STUDENT/ EIE/ACE, India
Original language: English
Copyright © 2017 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
In early days of Computers, Multiplication was implemented generally with a sequence of addition, subtraction and shift operations. Multiplier modules are common to many DSP applications. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. The various multiplier used are Array, Wallace and Vedic Multiplier. The Razor flip-flop is a timing fault detection technique that employs double sampling by the main and shadow Flip-Flops. Different types of multiplier are going to implement using XILINX ISE Design Suite 14.5 software and the performance will analysed with ordinary multiplier.
Author Keywords: Ripple Carry (RCA) Adder, Vedic Multiplier (VM), Urdhava Tiryakbhyam Sutra, Array Multiplication.
V.P. Krishnammal1, S. Anbuselvi2, and K. Janani3
1 ASST PROF/EIE /ACE, India
2 UG STUDENT/ EIE/ACE, India
3 UG STUDENT/ EIE/ACE, India
Original language: English
Copyright © 2017 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
In early days of Computers, Multiplication was implemented generally with a sequence of addition, subtraction and shift operations. Multiplier modules are common to many DSP applications. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. The various multiplier used are Array, Wallace and Vedic Multiplier. The Razor flip-flop is a timing fault detection technique that employs double sampling by the main and shadow Flip-Flops. Different types of multiplier are going to implement using XILINX ISE Design Suite 14.5 software and the performance will analysed with ordinary multiplier.
Author Keywords: Ripple Carry (RCA) Adder, Vedic Multiplier (VM), Urdhava Tiryakbhyam Sutra, Array Multiplication.
How to Cite this Article
V.P. Krishnammal, S. Anbuselvi, and K. Janani, “PERFORMANCE ANALYSIS OF VARIOUS MULTIPLIER USING VHDL,” International Journal of Innovation and Scientific Research, vol. 30, no. 3, pp. 343–348, May 2017.
