Volume 22, Issue 2, April 2016, Pages 356–363
T.R. Dineshkumar1, M. Anto Bennet2, V. Priyanka3, M. Priya4, and T. Ruby5
1 Assistant Professor, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
2 Professor, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
3 UG Student, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
4 UG Student, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
5 UG Student, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
A novel design methodology is to implement a secure DPA resistant crypto secured processor such as advanced encryption standard (AES) and triple data encryption standard (DES), by secure side-channel attacks, such as differential power analysis (DPA). The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. Dynamic logic is obfuscates the output waveforms and the circuit operation, which reducing the effectiveness of the DPA attack for mitigating DPA attacks for applications of secure integrated circuit (IC) design. A Penta MTJ gate that provides self-referencing, simple cascading, less voltage headroom downside in pre charge sense electronic equipment and low space. These types of gate is implemented in (PADDL). Different logic gates and different writing circuitry is required, but the sensing portion is remains same. Therefore, the information is deposited in the pinned layers using series or parallel combinations of transistors as per the logic storing in the Penta MTJ. The logic gate is authenticated by simulation at the 22nm technology node using a tanner tool.
Author Keywords: High-performance adiabatic dynamics differential logics (PADDL), Differential power Analysis (DPA) Attack, Penta MTJ, Magnetic tunnel junction, Magneto resistance, precharge sense amplifier (PCSA).
T.R. Dineshkumar1, M. Anto Bennet2, V. Priyanka3, M. Priya4, and T. Ruby5
1 Assistant Professor, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
2 Professor, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
3 UG Student, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
4 UG Student, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
5 UG Student, Department of Electronics and Communication Engineering, VEL TECH, Chennai-600062, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
A novel design methodology is to implement a secure DPA resistant crypto secured processor such as advanced encryption standard (AES) and triple data encryption standard (DES), by secure side-channel attacks, such as differential power analysis (DPA). The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. Dynamic logic is obfuscates the output waveforms and the circuit operation, which reducing the effectiveness of the DPA attack for mitigating DPA attacks for applications of secure integrated circuit (IC) design. A Penta MTJ gate that provides self-referencing, simple cascading, less voltage headroom downside in pre charge sense electronic equipment and low space. These types of gate is implemented in (PADDL). Different logic gates and different writing circuitry is required, but the sensing portion is remains same. Therefore, the information is deposited in the pinned layers using series or parallel combinations of transistors as per the logic storing in the Penta MTJ. The logic gate is authenticated by simulation at the 22nm technology node using a tanner tool.
Author Keywords: High-performance adiabatic dynamics differential logics (PADDL), Differential power Analysis (DPA) Attack, Penta MTJ, Magnetic tunnel junction, Magneto resistance, precharge sense amplifier (PCSA).
How to Cite this Article
T.R. Dineshkumar, M. Anto Bennet, V. Priyanka, M. Priya, and T. Ruby, “Design of Cascaded PADDL for DPA-Resistant Secure Integrated Circuits Using Penta Magnetic Tunnel Junction,” International Journal of Innovation and Scientific Research, vol. 22, no. 2, pp. 356–363, April 2016.
