JPEG2000 is a one of the popular image compression standard. The vital part of this standard JPEG2000 is Embedded Block Boding with Optimal Truncation (EBCOT). This block conserves major part of the processing time for performing compression operation. The EBCOT block consists of two components called bit-plane coder and MQ coder. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly subjugated to obtain a reconfigurable system. The current MQ coder architecture seeks ways to provide high throughput and minimum execution time with the decreasing the size and power consumption. In this study, various techniques used to implement the MQ coder block in FPGA are compared.