In this paper, a low power double gate TunnelFET (DGTFET) based flash memory cell is designed and its performance is studied through TCAD simulation. A DGTFET is converted into memory cell using floating gates. Its programming, erasing and reading operations are studied in the independently driven double gate (IDDG) mode through transient simulations. Out of the two gates one gate is used for “programming/Erasing” and the other gate is used for controlling the device characteristics dynamically and an application of a DC voltage to this gate reduces the reading delays.