Volume 30, Issue 3, May 2017, Pages 428–435
D. Ramya1, R. Vanithamani2, D. Yasmin3, and K. Elamathi4
1 PG Scholar, Dept of ECE, P.A.College of Engineering and Technology, Pollachi, India
2 PG Scholar, Dept of ECE, P.A.College of Engineering and Technology, Pollachi, India
3 PG Scholar, Dept of ECE, P.A.College of Engineering and Technology, Pollachi, India
4 Assistant Professor, Muthayammal Engineering College, Rasipuram, India
Original language: English
Copyright © 2017 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Built In Self Test (BIST) is used to test the working functions of IC circuit and it is one of the merit in IC’s to check all the working functions inside the IC circuit. And one of the other cons of BIST is it does not need any other additional device or circuit to test the functions of IC as it has additional power and additional circuit than other devices. Thus BIST reduces the power consumption of addition circuit by consuming considerable power. There is no solution to overcome the problem of consumption of larger power even there are vast methods to reduce consumption of power. But one of the best existing power reduction method in BIST is PRPG, as it gives pseudo Random patterns to test. But it also produce considerable power consumption due to toggling and repetition of patterns. Therefore we can use RTPG to overcome the drawbacks of toggling and repetition in PRPG. RTPG is the Random Test Pattern Generator uses Multiple in Input Signature Register (MIST) in order to reduce the repetition. So the power consumption can be reduced by reducing the pattern in our proposed system.
Author Keywords: BIST (Built In Self Test), PRPG, Multiple in input Signature Register, Design For Testability (DFT), RTPG, VLSI chips.
D. Ramya1, R. Vanithamani2, D. Yasmin3, and K. Elamathi4
1 PG Scholar, Dept of ECE, P.A.College of Engineering and Technology, Pollachi, India
2 PG Scholar, Dept of ECE, P.A.College of Engineering and Technology, Pollachi, India
3 PG Scholar, Dept of ECE, P.A.College of Engineering and Technology, Pollachi, India
4 Assistant Professor, Muthayammal Engineering College, Rasipuram, India
Original language: English
Copyright © 2017 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
Built In Self Test (BIST) is used to test the working functions of IC circuit and it is one of the merit in IC’s to check all the working functions inside the IC circuit. And one of the other cons of BIST is it does not need any other additional device or circuit to test the functions of IC as it has additional power and additional circuit than other devices. Thus BIST reduces the power consumption of addition circuit by consuming considerable power. There is no solution to overcome the problem of consumption of larger power even there are vast methods to reduce consumption of power. But one of the best existing power reduction method in BIST is PRPG, as it gives pseudo Random patterns to test. But it also produce considerable power consumption due to toggling and repetition of patterns. Therefore we can use RTPG to overcome the drawbacks of toggling and repetition in PRPG. RTPG is the Random Test Pattern Generator uses Multiple in Input Signature Register (MIST) in order to reduce the repetition. So the power consumption can be reduced by reducing the pattern in our proposed system.
Author Keywords: BIST (Built In Self Test), PRPG, Multiple in input Signature Register, Design For Testability (DFT), RTPG, VLSI chips.
How to Cite this Article
D. Ramya, R. Vanithamani, D. Yasmin, and K. Elamathi, “RTPG BASED BUILT IN SELF TEST FOR TEST COMPRESSION,” International Journal of Innovation and Scientific Research, vol. 30, no. 3, pp. 428–435, May 2017.
