Volume 28, Issue 1, December 2016, Pages 76–83
S.D. Jayavathi1 and A. Shenbagavalli2
1 Associate Professor, Department of Electronics and Communication Engineering, National Engineering college, Kovilpatti, India
2 Professor, Department of Electronics and Communication Engineering, National Engineering college, Kovilpatti, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
JPEG2000 is a one of the popular image compression standard. The vital part of this standard JPEG2000 is Embedded Block Boding with Optimal Truncation (EBCOT). This block conserves major part of the processing time for performing compression operation. The EBCOT block consists of two components called bit-plane coder and MQ coder. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly subjugated to obtain a reconfigurable system. The current MQ coder architecture seeks ways to provide high throughput and minimum execution time with the decreasing the size and power consumption. In this study, various techniques used to implement the MQ coder block in FPGA are compared.
Author Keywords: MQ coder, EBCOT, JPEG 2000 Standard, FPGA.
S.D. Jayavathi1 and A. Shenbagavalli2
1 Associate Professor, Department of Electronics and Communication Engineering, National Engineering college, Kovilpatti, India
2 Professor, Department of Electronics and Communication Engineering, National Engineering college, Kovilpatti, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
JPEG2000 is a one of the popular image compression standard. The vital part of this standard JPEG2000 is Embedded Block Boding with Optimal Truncation (EBCOT). This block conserves major part of the processing time for performing compression operation. The EBCOT block consists of two components called bit-plane coder and MQ coder. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly subjugated to obtain a reconfigurable system. The current MQ coder architecture seeks ways to provide high throughput and minimum execution time with the decreasing the size and power consumption. In this study, various techniques used to implement the MQ coder block in FPGA are compared.
Author Keywords: MQ coder, EBCOT, JPEG 2000 Standard, FPGA.
How to Cite this Article
S.D. Jayavathi and A. Shenbagavalli, “FPGA Implementation of MQ Coder in JPEG 2000 Standard - A Review,” International Journal of Innovation and Scientific Research, vol. 28, no. 1, pp. 76–83, December 2016.
