Volume 22, Issue 2, April 2016, Pages 275–282
S. Arrthi1, R. Ambika2, and K.K. Nagarajan3
1 PG Scholar, ECE Department, SSN College of Engineering, Rajiv Gandhi Salai, Kalavakkam – 603110, India
2 JRF, IT Department, SSN College of Engineering, Rajiv Gandhi Salai, Kalavakkam – 603110, India
3 Professor, ECE Department, SSN College of Engineering, Rajiv Gandhi Salai, Kalavakkam – 603110, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
In this paper, a low power double gate TunnelFET (DGTFET) based flash memory cell is designed and its performance is studied through TCAD simulation. A DGTFET is converted into memory cell using floating gates. Its programming, erasing and reading operations are studied in the independently driven double gate (IDDG) mode through transient simulations. Out of the two gates one gate is used for “programming/Erasing” and the other gate is used for controlling the device characteristics dynamically and an application of a DC voltage to this gate reduces the reading delays.
Author Keywords: Tunnel FET, Flash memory, Double gate, IDDG.
S. Arrthi1, R. Ambika2, and K.K. Nagarajan3
1 PG Scholar, ECE Department, SSN College of Engineering, Rajiv Gandhi Salai, Kalavakkam – 603110, India
2 JRF, IT Department, SSN College of Engineering, Rajiv Gandhi Salai, Kalavakkam – 603110, India
3 Professor, ECE Department, SSN College of Engineering, Rajiv Gandhi Salai, Kalavakkam – 603110, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
In this paper, a low power double gate TunnelFET (DGTFET) based flash memory cell is designed and its performance is studied through TCAD simulation. A DGTFET is converted into memory cell using floating gates. Its programming, erasing and reading operations are studied in the independently driven double gate (IDDG) mode through transient simulations. Out of the two gates one gate is used for “programming/Erasing” and the other gate is used for controlling the device characteristics dynamically and an application of a DC voltage to this gate reduces the reading delays.
Author Keywords: Tunnel FET, Flash memory, Double gate, IDDG.
How to Cite this Article
S. Arrthi, R. Ambika, and K.K. Nagarajan, “A Novel Double Gate Tunnel FET based Flash Memory,” International Journal of Innovation and Scientific Research, vol. 22, no. 2, pp. 275–282, April 2016.
