Volume 11, Issue 1, October 2014, Pages 117–125
Fathima Nishah P1 and Ruksana Maitheen2
1 Applied Electronics, Ilahia college of engineering and Technology, Ernakulam, Kerala, India
2 Electronics and Communication, Ilahia college of engineering and Technology, Ernakulam, Kerala, India
Original language: English
Copyright © 2014 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
In this paper we present two different architectures for modulo 2n+1 adder and by using this an efficient FFT computation is performed. One of the architecture is based on a sparse carry computation unit in which only some of the carries are computed. In this an inverted circular idempotency property of the parallel prefix carry operator is used and its efficiency is increased by a new prefix operator. The resulting adders will be having less area and power. The second architecture is derived by modifying modulo 2n-1 adders with minor hardware overhead. By using this adder we can implement FFT processor with improved performance.
Author Keywords: Parallel prefix carry computation, Modulo addition, Diminished-1 addition, inverted circular idempotency, IEAC adder.
Fathima Nishah P1 and Ruksana Maitheen2
1 Applied Electronics, Ilahia college of engineering and Technology, Ernakulam, Kerala, India
2 Electronics and Communication, Ilahia college of engineering and Technology, Ernakulam, Kerala, India
Original language: English
Copyright © 2014 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
In this paper we present two different architectures for modulo 2n+1 adder and by using this an efficient FFT computation is performed. One of the architecture is based on a sparse carry computation unit in which only some of the carries are computed. In this an inverted circular idempotency property of the parallel prefix carry operator is used and its efficiency is increased by a new prefix operator. The resulting adders will be having less area and power. The second architecture is derived by modifying modulo 2n-1 adders with minor hardware overhead. By using this adder we can implement FFT processor with improved performance.
Author Keywords: Parallel prefix carry computation, Modulo addition, Diminished-1 addition, inverted circular idempotency, IEAC adder.
How to Cite this Article
Fathima Nishah P and Ruksana Maitheen, “Design of FFT Processor using Modified Modulo 2n+1 Adder,” International Journal of Innovation and Scientific Research, vol. 11, no. 1, pp. 117–125, October 2014.
