Volume 25, Issue 2, July 2016, Pages 646–653
Erulappan Sakthivel1, Veluchamy Malathi2, Muruganantham ARUNRAJA3, and Govindaraj Perumalvignesh4
1 Department of Electrical and Electronics Engineering, The Siliconharvest, Madurai, Tamilnadu, India
2 Electrical and Electronics Engineering, Anna University Regional Centre Madurai, Madurai, Tamil Nadu, India
3 Department of Electrical and Electronics Engineering, The Siliconharvest, Madurai, Tamilnadu, India
4 Department of Electrical and Electronics Engineering, The Siliconharvest, Madurai, Tamilnadu, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Bilateral filters use a wide range of medical and industrial applications. The limitations of conventional bilateral filter architecture are having a minimum kernel size and constant delay. This constant delay depends on two modules available in architecture such as the width of the image and sum of processing elements. Due to the inputs variation the kernel size can extent which may affect overall performance in terms of all the image quality assessment and performance in FPGA level (scalability, latency, power consumption). To evade this problem Low power, high speed FPGA based Novel Approach for Bilateral filter (NABI) are introduced. This NABI consists of Structure Shared Architecture (SSA), Master Control Unit (combination of intensity calculator and graph theory based traffic estimator), kernel based clock unit and Reconfigurable server. These components are described on the register transfer level implemented in VHDL. Depends upon the size of the kernel the reconfiguration is taking place via reconfigurable server. The intensity calculator is used to estimate the intensity of image and that intensity value is placed in normalization block to achieve better PSNR and MSE. This proposed NABI is implemented in a Virtex-5VLX50-1 device. The performance results in terms of FPGA level 31.69% slice reduction, 49.51% frame rate improvement, 28.96% power reduction and 50% latency reduction are achieved. The image quality assessment is also observed and compared with conventional algorithms. Thus, NABI work achieves better outcome than conventional work.
Author Keywords: Bilateral Filter, image processing, real time processing, Field Programmable Gate Array (FPGA).
Erulappan Sakthivel1, Veluchamy Malathi2, Muruganantham ARUNRAJA3, and Govindaraj Perumalvignesh4
1 Department of Electrical and Electronics Engineering, The Siliconharvest, Madurai, Tamilnadu, India
2 Electrical and Electronics Engineering, Anna University Regional Centre Madurai, Madurai, Tamil Nadu, India
3 Department of Electrical and Electronics Engineering, The Siliconharvest, Madurai, Tamilnadu, India
4 Department of Electrical and Electronics Engineering, The Siliconharvest, Madurai, Tamilnadu, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
Bilateral filters use a wide range of medical and industrial applications. The limitations of conventional bilateral filter architecture are having a minimum kernel size and constant delay. This constant delay depends on two modules available in architecture such as the width of the image and sum of processing elements. Due to the inputs variation the kernel size can extent which may affect overall performance in terms of all the image quality assessment and performance in FPGA level (scalability, latency, power consumption). To evade this problem Low power, high speed FPGA based Novel Approach for Bilateral filter (NABI) are introduced. This NABI consists of Structure Shared Architecture (SSA), Master Control Unit (combination of intensity calculator and graph theory based traffic estimator), kernel based clock unit and Reconfigurable server. These components are described on the register transfer level implemented in VHDL. Depends upon the size of the kernel the reconfiguration is taking place via reconfigurable server. The intensity calculator is used to estimate the intensity of image and that intensity value is placed in normalization block to achieve better PSNR and MSE. This proposed NABI is implemented in a Virtex-5VLX50-1 device. The performance results in terms of FPGA level 31.69% slice reduction, 49.51% frame rate improvement, 28.96% power reduction and 50% latency reduction are achieved. The image quality assessment is also observed and compared with conventional algorithms. Thus, NABI work achieves better outcome than conventional work.
Author Keywords: Bilateral Filter, image processing, real time processing, Field Programmable Gate Array (FPGA).
How to Cite this Article
Erulappan Sakthivel, Veluchamy Malathi, Muruganantham ARUNRAJA, and Govindaraj Perumalvignesh, “NABI: Low power, high speed FPGA based Novel Approach for Bilateral filter,” International Journal of Innovation and Scientific Research, vol. 25, no. 2, pp. 646–653, July 2016.
