Volume 22, Issue 2, April 2016, Pages 293–303
M. Manimaraboopathy1, M. Anto Bennet2, B. Sumitha3, P. Nithyasri4, and R. Pavithra5
1 Assistant Professor, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
2 Professor, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
3 UG Student, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
4 UG Student, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
5 UG Student, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Power has become a burning issue in modern VLSI design and integrated circuits; the power consumed by clocking gradually takes a dominant part. The proposed system provided a design to reduce the clock tree power by replacing some flip-flops with fewer multi-bit flip-flops, and also reduces the total power consumption. First, it perform a co-ordinate transformation to identify those flip flops that can be merged and also identify their legal regions in a library. Next step is to build a combination table to enumerate possible combinations of flip-flops provided by the library. The last step is to merge flip-flops in a hierarchical way. Besides power reduction, the objective of minimizing the total wire length is also considered. The time complexity of the proposed algorithm is less than the time complexity of the existing algorithm. According to the experimental results, the proposed algorithm significantly reduces the clock power by 27.9% and area reduced by 18.5%. The running time is very short. By using this method the low power consumed IC’s can be manufactured using CMOS technologies.
Author Keywords: Single & Double bit flip flops, Legal Placement Region, Flip flop Merging Power Report.
M. Manimaraboopathy1, M. Anto Bennet2, B. Sumitha3, P. Nithyasri4, and R. Pavithra5
1 Assistant Professor, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
2 Professor, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
3 UG Student, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
4 UG Student, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
5 UG Student, Department of Electronics and Communication Engineering, VELTECH, Chennai-600062, India
Original language: English
Copyright © 2016 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
Power has become a burning issue in modern VLSI design and integrated circuits; the power consumed by clocking gradually takes a dominant part. The proposed system provided a design to reduce the clock tree power by replacing some flip-flops with fewer multi-bit flip-flops, and also reduces the total power consumption. First, it perform a co-ordinate transformation to identify those flip flops that can be merged and also identify their legal regions in a library. Next step is to build a combination table to enumerate possible combinations of flip-flops provided by the library. The last step is to merge flip-flops in a hierarchical way. Besides power reduction, the objective of minimizing the total wire length is also considered. The time complexity of the proposed algorithm is less than the time complexity of the existing algorithm. According to the experimental results, the proposed algorithm significantly reduces the clock power by 27.9% and area reduced by 18.5%. The running time is very short. By using this method the low power consumed IC’s can be manufactured using CMOS technologies.
Author Keywords: Single & Double bit flip flops, Legal Placement Region, Flip flop Merging Power Report.
How to Cite this Article
M. Manimaraboopathy, M. Anto Bennet, B. Sumitha, P. Nithyasri, and R. Pavithra, “Implementation of High Speed & Low Power Approach by Designing Multi-Bit Flip-Flops,” International Journal of Innovation and Scientific Research, vol. 22, no. 2, pp. 293–303, April 2016.
